Method and apparatus for receiving GPS/GLONASS signals

ABSTRACT

A method of processing received L1 and L2 spread spectrum signals is disclosed. In one embodiment, the method comprises i) locally generating replicas of a known P-code, wherein each of the received signals includes a unique frequency carrier with the known pseudo-random P-code and an unknown code modulated thereon, ii) making the code replicas available at different relative phases, iii) demodulating the received L1 and L2 signals with replicas of the P-code, iv) repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code, and v) correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.

RELATED APPLICATIONS

This application is a continuation application which claims priorityunder 35 U.S.C. §120 from U.S. patent application Ser. No. 11/139,128,filed May 26, 2005, and which is incorporated by reference. U.S. patentapplication Ser. No. 11/139,128 also claimed priority from U.S. patentapplication Ser. No. 09/196,658, filed Nov. 19, 1998, now U.S. Pat. No.6,967,992, issued Nov. 22, 2005, and which is also incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic system and its componentsand to methods of operating the system and its components for receivingspread spectrum signals, for example, signals from a global positioningsystem such as Global Positioning System (GPS) and/or Global OrbitingNavigation Satellite System (GLONASS).

2. Description of the Related Technology

An increasing number of applications and systems for communicatinginformation nowadays make use of the spread spectrum technique. Thespread spectrum technique is a digital modulation technique in which adigital signal is spread over a wide frequency band so that it has anoise-like spectrum. This can be done by breaking up or “chopping” eachdata bit of the digital signal into multiple sub-bits (commonly calledchips) that are then modulated and up-converted to a carrier frequency.The chopping may be done by multiplying the digital information signalwith a so-called pseudo-random code or PN code. By using orthogonalcodes for different communication links, the same frequency band can beused for different simultaneous communication links.

Using the same PN code as the transmitter, a receiver can correlate thereceived, spread signal and reconstruct the data signal while otherreceivers that use other codes or other transmission techniques cannot.One of the advantages of using the spread spectrum communicationtechnique is the robustness to narrow band interference signals. Becausespread-spectrum receivers are rapidly being introduced in applicationsand systems meant for the consumer markets, the cost of the receiversystem is a major determining factor in order to remain competitive.

A specific class of spread spectrum systems are devices and receiversfor position determination. Such devices are gaining importance for boththe consumer market and for high precision applications. Most of theexisting systems are based on the American Global Positioning System(GPS). Because this is also a military system, a precise positiondetermination can be made difficult by the satellite operatordeliberately introducing errors (called “anti-spoofing”). Moreover, inmany areas the number of visible satellites can be too limited todetermine an accurate position. These two problems can be reduced byalso using a second positioning system such as the Russian GlobalOrbiting Navigation Satellite System (GLONASS) system.

Combined GPS and GLONASS receivers have been reported, e.g., S. Riley,N. Howard, E. Aardoom, R. Daly, and P. Silvestrin, in “A combinedGPS/GLONASS high precision receiver for space applications,” ION-GPS 95,Palm Springs, USA, September 1995, or Japanese patent application JP7128423-950519, “Receiver Common to GPS and GLONASS.”

A GPS receiver is disclosed in U.S. Pat. No. 5,293,170 that can be usedwith P-code modulated signals, which have been modulated with an unknowncode. Implementations of this known device require a lot of registers.

U.S. Pat. No. 5,600,670 describes a GPS receiver that includes ahierarchical chain of channel modules which includes slave modules and amaster module. The known system does not provide sufficient flexibility.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

One aspect of the invention provides a method of processing received L1and L2 spread spectrum signals, wherein each of the signals includes aunique frequency carrier with a known pseudo-random code modulatedthereon, each L1 and L2 signal being converted into a plurality ofdigital signals, the method comprising: i) locally generating a singlereplica of the known code, ii) making the code replica available atdifferent relative phases, iii) first demodulating the converted L1 andL2 signals with the single replica of the known code without anysubstantial delay, the first demodulated signal being associated withthe L1 signal, iv) second demodulating the converted L1 and L2 signalswith the generated replica of the known code from one of the taps of thedelay line, the second demodulated signal being associated with the L2signal, v) selectably switching the converted L1 and L2 signals for thefirst demodulation and selectably switching the converted L1 and L2signals for the second demodulation, vi) repetitively and separatelyintegrating the demodulated L1 and L2 signals over a time period, andvii) adjusting the phases of the locally generated code replicasrelative to the incoming L1 and L2 signals in order to maximize thepower of the integrated demodulated L1 and L2 signals.

Another aspect of the invention provides an apparatus for processingreceived L1 and L2 spread spectrum signals, wherein each of the signalsincludes a unique frequency carrier with a known pseudo-random P-codeand an unknown code modulated thereon, the apparatus comprising: i) agenerator of replicas of the known P-code, ii) a delay line configuredto make the known P-code replicas available at different relativephases, iii) a first demodulator, connected to the generator, configuredto demodulate one of the received L1 and L2 signals with one of theknown P-code replicas, iv) a second demodulator configured to demodulatethe other of the received L1 and L2 signals with one of the known P-codereplicas, v) a first integrator configured to repetitively andseparately integrate the demodulated one of the L1 and L2 signals overtime periods related to the unknown code, vi) a second integratorconfigured to repetitively and separately integrate the demodulatedother of the L1 and L2 signals over time periods related to the unknowncode, and vii) a correlator configured to correlate the first integratoroutput with the second integrator output.

Another aspect of the invention provides an apparatus for processingreceived L1 and L2 spread spectrum signals, wherein each of the signalsincludes a unique frequency carrier with a known pseudo-random codemodulated thereon, each L1 and L2 signal being converted into aplurality of digital signals, the apparatus comprising: i) a generatorconfigured to locally generate a single replica of the known code, ii) adelay line wherefrom the known P-code replicas are available atdifferent relative phases thereof, wherein the single replica of theknown code is applied to the delay line, iii) a first demodulatorconfigured to first demodulate the converted L1 and L2 signals with thesingle replica of the known code without any substantial delay, thefirst demodulated signal being associated with the L1 signal, iv) asecond demodulator configured to second demodulate the converted L1 andL2 signals with the generated replica of the known code from one of thetaps of the delay line, the second demodulated signal being associatedwith the L2 signal, v) a switch configured to selectably switch theconverted L1 and L2 signals for the first demodulation and selectablyswitch the converted L1 and L2 signals for the second demodulation, vi)an integrator configured to repetitively and separately integrate thedemodulated L1 and L2 signals over a time period, and vii) a phaseadjuster configured to adjust the phases of the locally generated codereplicas relative to the incoming L1 and L2 signals in order to maximizethe power of the integrated demodulated L1 and L2 signals.

Still another aspect of the invention provides a method of processingreceived L1 and L2 spread spectrum signals, wherein each of the signalsincludes a unique frequency carrier with a known pseudo-random P-codeand an unknown code modulated thereon, the method comprising: i) locallygenerating replicas of the known P-code, ii) making the code replicasavailable at different relative phases, iii) demodulating the receivedL1 and L2 signals with replicas of the P-code, iv) repetitively andseparately integrating the demodulated L1 and L2 signals over timeperiods related to the unknown code, and v) correlating an integrationresult for one of the L1 and L2 signals with an integration result forthe other of the L1 and L2 signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing the major components of aspread spectrum receiver according to one embodiment of the presentinvention.

FIG. 2 illustrates a schematic representation of a part of thecorrelator unit in accordance with one embodiment of the presentinvention.

FIG. 3 illustrates a schematic representation of a channel matrix inaccordance with an embodiment of the present invention.

FIG. 4 illustrates a schematic representation of a CA-channel module inaccordance with an embodiment of the present invention.

FIG. 5 illustrates a schematic representation of a hierarchical chain ofCA-channel modules in accordance with an embodiment of the presentinvention.

FIG. 6 illustrates a schematic representation of a dual frequencychannel in accordance with an embodiment of the present invention.

FIGS. 7 a and 7 b illustrate schematic representations of slavingcontrol circuits for a CA-channel module and a CaP-channel module,respectively, in accordance with an embodiment of the present invention.

FIG. 8 illustrates a schematic representation of a code delay line unitin accordance with an embodiment of the present invention.

FIGS. 9 a and 9 b illustrate two examples of three channel modules withslaved code delay lines in accordance with an embodiment of the presentinvention.

FIG. 10 illustrates a schematic representation of a correlator unit inaccordance with an embodiment of the present invention.

FIG. 11 illustrates a schematic representation of a CA-code integratormodule in accordance with an embodiment of the present invention.

FIG. 12 illustrates a schematic representation of a CaP-code integratormodule in accordance with an embodiment of the present invention.

FIG. 13 illustrates a schematic representation of a CaP-code integratormodule including a Y-code estimator in accordance with an embodiment ofthe present invention.

FIG. 14 illustrates a schematic representation of a Y-code estimator inaccordance with an embodiment of the present invention.

FIG. 15 illustrates schematic representation of a P-code unit inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS

Definitions

Channel: The functionality or hardware required to track onepseudo-noise code on a single frequency, e.g., a navigation code such asCA on L1 of SV3 or P on L2 of SV19. For example, not all channels of theAdvanced GPS/GLONASS receiver (AGGR) need be identical in functionality.For instance, some may only be able to track the CA-code, others alsothe P-code. Some can operate as a master in a master-slaveconfiguration, and some not.

Dual-frequency channel: The functionality and hardware needed to trackall three ranging signals transmitted by one GPS or GLONASS satelliteare placed on one carrier (L1) and the same P-code is placed on a secondcarrier (P on L2). A dual-frequency channel is formed by grouping threesingle-frequency channels.

Observables: Information read from the AGGR, except the correlationvalues (i.e. carrier frequency cycle counter, phase and code carrierfrequency cycle counter and phase for each channel).

Pseudorange measurements: Synonym for code-phase measurements.

RF conditioning input: The input to which the antenna is connected.

Measurement epoch signal: Periodic strobe signal which controls updatingof observables, common to all channels.

Integration epoch signal: Periodic strobe signal which controls updatingof frequency and/or phase of internal code and carrier replica signals,individual for each channel. This signal also updates correlator outputregisters.

Antenna switch epoch signal: Strobe signal which controls updating ofcorrelator output registers.

Code epoch signal: Periodic strobe signal which indicates a uniquepattern (corresponding to the all-ones state of the code generator shiftregister) in the generated or received pseudo-random noise code.

GNSS signals: Combination of GPS, GLONASS and various augmentationsignals, e.g., EGNOS, WAAS, MTSAT.

Complex signal: A signal split into in-phase (I) and quadrature (Q)components.

Interchannel bias: Mean error between two channels tracking the samesatellite signal.

Bit numbering and naming conventions: Bussed signals are indexed fromthe least significant (LSB) to the most significant bit (MSB). The LSBhas index 0 while the MSB of a vector of length N has index N-1. Asuffix of “N” to a signal name indicates that a signal is active low.For example, ResetN is an active low signal.

List of Abbreviations:

-   -   ADC: Analogue to Digital Converter    -   ADSP21020: Analog Devices Digital Signal Processor 21020    -   AGC: Automatic Gain Control    -   AGGR: Advanced GPS/GLONASS receiver    -   AGGA: Advanced GPS/GLONASS ASIC    -   AOCS: Attitude and Orbit Control System    -   AS: Anti-Spoofing, technique by which the GPS P-code is        encrypted    -   ASIC: Application Specific Integrated Circuit    -   CA-code: Coarse Acquisition code    -   CaP-channel: Channel that can process CA- and P-codes    -   CDMA: Code Division Multiple Access    -   DAC: Digital to Analogue Converter    -   DSP: Digital Signal Processing    -   E: Early correlation    -   EGNOS: European Geostationary Navigation Overlay System    -   EOW: End of Week    -   ERC32: Embedded Real-time Core, 32-bit Sparc microprocessor    -   GLONASS: Global Orbiting Navigation Satellite System    -   GNSS: Global Navigation Satellite Systems    -   GPS: Global Positioning System    -   I: In-phase    -   IF: Intermediate Frequency    -   IO: Input-Output    -   L: Late correlation    -   L1: Carrier frequency (1575.42 MHz for GPS, 1602.0+ 9/16*ch MHz        for GLONASS)    -   L2: Carrier frequency (1227.6 MHz for GPS, 1246.0+ 7/16*ch MHz        for GLONASS)    -   LFSR: Linear Feedback Shift Register    -   LSB: Least Significant Bit    -   MSB: Most Significant Bit    -   MSPS: Mega Samples Per Second    -   MTSAT: Mobile Transport Satellite system    -   NCO: Numerically Controlled Oscillator    -   P: Punctual correlation    -   PCB: Printed Circuit Board    -   P-code: Precision code    -   PLL: Phase-Locked Loop    -   PN-code: Pseudo-Noise code    -   POD: Precise Orbit Determination    -   PRN: Pseudo-Random Noise    -   Q: Quadrature    -   RF: Radio-Frequency    -   SA: Selective Availability    -   SM: Sign/Magnitude    -   SNR: Signal-to-Noise Ratio    -   SV: Space Vehicle    -   W-code: Code used to encrypt the GPS P-code to form the Y-code    -   WAAS: Wide Area Augmentation System    -   Y-code: Encrypted GPS P-code        Description of Certain Embodiments

The present invention will be described with reference to specificembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. Further, the presentinvention will mainly be described with reference to global positioningand navigation systems such as GLONASS or GPS but the present inventionis not limited thereto but only by the claims. In particular, thepresent invention may find application with spread spectrumcommunications systems generally, in particular with direct sequenceCDMA (DS-CDMA) systems. In particular, the functional specification forthe design of an advanced GPS and/or GLONASS receiver (AGGR) isdisclosed. The AGGR is preferably fabricated including at least onesub-system implemented as an application specific integrated circuit(ASIC). The ASIC implementation of the AGGR will be referred to as theAGGA. The AGGR and particularly the ASIC (AGGA) may be used in a varietyof combined GPS/GLONASS receivers for a multitude of applicationsincluding, as a non-limiting list, synchronization of mobile telephonesystems, personal location devices, high precision scientificinstruments and satellite attitude and orbit control systems.

The main functional units of an AGGR 100 in accordance with anembodiment of the present invention are shown schematically in FIG. 1.The AGGR 100 may comprise a linear arrangement of a microprocessor 101,a digital correlator 102, an analog front-end 103 and an antenna orantennae, e.g., an antenna array, 104. The microprocessor 101 runs theapplications software and controls the operation of the AGGR 100. Thecorrelator 102 comprises a number of channels or channel modules whichcan acquire and/or track spread spectrum signals, e.g., those receivedfrom a global positioning satellite. The correlator 102 may have thecapability of multipath mitigation and/or calibration and/or fastacquisition. The front-end 103 converts the RF signals captured by theantenna 104 into time-discrete digital signals which can be used by thecorrelator 102. A suitable front-end unit 103 is known from co-pendingEuropean Patent Application No. 97870164.7 “Method and Apparatus forreceiving a converting spread spectrum signals” which is incorporatedhereby by reference.

In accordance with one embodiment of the present invention, thecorrelator 102 may include an AGGA 10 but the present invention is notlimited thereto and other forms of circuits may be used, e.g., PCB's. Aschematic functional block diagram of an AGGA 10 in accordance with oneembodiment of the present invention is shown in FIG. 2. The AGGA 10comprises eight main functional blocks: a front-end interface 2 whichinterfaces with the front end 103, a channel matrix 3, a time basegenerator 4, a clock generator 5, and a microprocessor interface 6 whichinterfaces with the receiver microprocessor 101, an interrupt controller7, a general purpose 10 port 8 and an antenna switch controller 9. TheResetN input signal is distributed to all modules 1-9. The modules 1-9may be connected together via an internal bus I.

In the following description reference may be made to registers. Theseregisters are not shown in the drawings but may be located on-chip,i.e., on the same chip as the AGGA 10 ASIC. A memory map may be providedso that the address location of each register may be known to themicroprocessor 101 independent of the specific design of thismicroprocessor 101.

The front-end interface 2 accepts digitized Intermediate Frequency (IF)input signals ADCIn0-7 from the analog front-end 103. The IF signal, forinstance, can be real or complex. When real, the signal may betransformed into an In-Phase (I) and a Quadrature (Q) value anddown-converted by a fixed frequency equal to a quarter of the samplingfrequency. When the input IF signal is complex, it is represented as anIn-Phase (I) and Quadrature (Q) value on two adjacent inputs. Thedown-conversion stage is then bypassed. AGGA 10 may be adapted tosupport a multitude of input formats, e.g., sign/magnitude, unsigned,two's complement and three-level comparator output. Furthermore, anestimate of the input energy (signal-plus-noise) may be measured to beused for automatic gain control (AGC) purposes, for instance, a signallevel detector (not shown) may estimate the signal-plus-noise power ofthe I or Q branch of a complex signal and may be time shared by allinputs.

The channel matrix 3 contains a plurality (N) of independent channels,and may find general use in despreading spread-spectrum signals. Inparticular, in accordance with one embodiment of the present invention,each channel may be capable of L1 or L2 CA-code processing. Thesechannels can also be configured into groups of three to form up to N/3independent dual-frequency tracking channels capable of tracking CA-codeon L1 or L2 and P-code on L1 and L2. Furthermore, channels can begrouped in several other ways to support functions such as fastacquisition, attitude determination by means of interferometric carrierphase measurements and multipath mitigation.

The number of channels N in an AGGA 10 is determined by how many can beintegrated in the chosen technology. Each channel can be configuredindependently to track a GNSS signal. Dual-frequency channels supportP-code and Y-code tracking. At the end of each measurement epoch,carrier and code phase values for all channels are latched into a set ofobservable registers (not shown). At the end of the integration epoch(individual for each channel) the code correlation values are latchedinto a set of correlation registers (not shown). The correlation valuesare used by the receiver firmware to close the tracking loops, includingcarrier and code phase error computations, application of loop filters,and estimation of signal and noise amplitude. The observables are usedby the receiver firmware to derive the position, time, velocity and insome cases attitude. The measure epoch is provided by the time basegenerator 4 and is common for all channels.

The time base generator 4 preferably produces three periodic strobesignals EpochClk, MEO and OnePPS for accurate receiver time-keeping andobservable measurements. The EpochClk output has a nominal frequency of1 kHz and is the clock signal for the integration level epochgeneration, the measurement epoch generation and the antenna switchcontroller. The measurement epoch output MEO is asserted to indicate theend of each measurement epoch. The measurement epoch input MEI acceptsthe MEO strobe from another AGGA 10 to enable synchronization of theobservable measurements in configurations with more than one AGGA 10.The time base generator 4 also generates a one-pulse-per-second (OnePPS)signal to which external equipment can be synchronized.

The clock generator 5 produces one internal clock signal CoreClk andthree external clock signals SampleClk, GenClk and ProcClk, all derivedfrom an external clock. For instance, the AGGA 10 can generate clocksignals for the ADC's and the internal channel matrix 3, a GP2010front-end as made by GEC Plessey Semiconductors, UK and the receivermicroprocessor 101. The different clock frequencies can be programmedindividually. Three dedicated inputs are provided to program the clockdivision ratio of the microprocessor clock.

A microprocessor 101 can access the AGGA 10 through the microprocessorinterface 6. The AGGA 10 may behave as a generic memory-mappedperipheral. An internal address decode (not shown) may be provided inthe microprocessor interface 6, which allows the microprocessor 101 toaddress up to 4 AGGA's 10 using only a single chip select line. Twodedicated inputs are provided to select the valid address range of theAGGA 10. The interface 6 is preferably directly compatible with theAnalog Devices ADSP21020 and the ERC32 Spare chip set. It is 32-bit wideand does not require wait-states at the specified processor clockfrequencies of 20 MHz and 14 MHz for the ADSP21020 and ERC32,respectively, under the condition that the CoreClk frequency of the AGGA10 exceeds the microprocessor clock frequency. Otherwise, themicroprocessor 101 must insert wait-states to ensure that a read orwrite operation exceeds the CoreClk cycle time.

When various modules within the AGGA 10 require action by themicroprocessor 101, this can be signaled through interrupt requests. TheAGGA interrupt controller 7 receives these interrupt requests, storesthem in an interrupt status register (not shown) and generates anexternal interrupt request. To connect multiple AGGA's 10 with a singleinterrupt signal to the microprocessor 101 the interrupt controller 7may have two external interrupt inputs, allowing a number of AGGA's 10to be connected, e.g., as a binary tree.

The parallel IO interface 8 supports functionality such as systemmonitoring and control functions, e.g., monitoring lock indicators ofthe external down-converter frequency synthesizers, or power-down ofexternal circuitry. The output port 8 can, for example, be used forcontrolling parallel DACs for the front-end AGC functions. All IO pinsare preferably uni-directional to prevent accidental short-circuits dueto incorrect programming of the direction of IO drivers.

The antenna switch controller 9 provides means to control antennaswitching for up to four antenna units 104, for instance, in a hybridparallel-multiplex attitude determination GNSS receiver 100. It alsoproduces an antenna switch epoch strobe which signals an antenna switchevent and which is used to store correlator readings of all channelsconfigured as slave channels. In configurations with more than one AGGA10 only the antenna switch controller 9 of one master AGGA 10 need beenabled, while all other slave AGGA's 10 preferably use the AntennaSwitch Epoch Output (ASE) of the master AGGA 10 to control theirrespective correlators 102.

A structure of the channel matrix 3 in accordance with one embodiment ofthe present invention is shown schematically in FIG. 3. The channelmatrix 3 includes a plurality of processing channels 30 to 41. Twelvechannels are shown but the invention is not limited thereto. Allchannels 30 to 41 preferably have identical functionality for CA-codetracking. Any channel 30-41 can also be configured to processunmodulated input signals, a feature which is provided for thecalibration of RF front-end group delay variations. Channels 30, 33, 36,39 which can only track the CA-code are called CA-channels, whileCaP-channels 31, 32, 34, 35, 37, 38, 40, and 41 have additionalfunctionality to enable them to track also P-code or Y-code modulatedsignals. A separate P-code unit 42-45 per dual-frequency channelgenerates the replica P-code for the pair of CaP-channels, e.g., 37, 38,when one CA-channel 36 and two CaP-channels 37, 38 are grouped to form adual-frequency channel (one column of the channel matrix 3 as shown).

The channels 30-41 can be selectively slaved as indicated by the dashedor solid lines in FIG. 3. Slaving means at least that certain signals orsignal parameters generated by the master channel (usually a CA-channel)are used by the next channel in the sequence or chain. Channels may behierarchically chained together. For instance, for rapid acquisition allthe CA-channels 30, 33, 36, 39 may be slaved together, the timing forthe despreading operation used by one channel being passed on to thenext channel in the sequence which adds a delay, attempts a correlationwith the received signal and passes the delayed timing to the nextchannel and so on. By slaving, unnecessary re-calculation of signalparameters already calculated or used in the channel before may beavoided. In particular the speed of acquisition can be increased.

The operation of the channel matrix 3 is preferably entirely controlledby the external microprocessor 101. The basic functions of each channel30-41 are: selection of one of eight complex output signals IQ0-7 fromthe front-end interface 2, down-conversion of the selected complexsign-magnitude signals IQ0-7 to baseband, despreading of the complexbaseband signals with the on-chip generated CA or P replica code andintegration over a programmable time interval. The result of theseintegrations is the correlation values. Together with the observables,which are the carrier and code frequency and phase measurements, theyare the outputs of the channels 30-41.

A CA-channel 30, 33, 36, 39 preferably can process L1 or L2 CA-codemodulated GNSS signals but not P-code or Y-code modulated signals. Ablock diagram of a CA-channel 30 in accordance with an embodiment of thepresent invention is shown schematically in FIG. 4. An input selector302 selects one of the eight complex front-end interface output signalsIQ0-7 with sample rate equal to the CoreClk rate. In an image rejectmixer 305 any residual carrier frequency is removed by rotating theselected complex signal by an angle determined by a carrier generator304, resulting in a complex baseband signal. A correlator unit 307 thendespreads this signal using three CA-code sequence combinations E, P andL (early, punctual and late) and integrates the result during aprogrammable integration period. Hence, the correlator unit 307 includessix accumulators: three for each of the I and Q branches (not shown).The outputs of the correlator unit 307 are the correlation values. Inthe case of hybrid parallel-multiplex attitude determination, theintegration period can be controlled by the antenna switch epoch (ASE)strobe.

The three CA-code sequence E, P and L are derived from a single CA-codesequence generated by the CA-code unit 306. The delays between the E,the P and the L sequences are determined by the settings of the CA-codedelay-line unit 308. The CA-code chip rate is determined by the codenumerically controlled oscillator (NCO, not shown) of the CA-code unit306. The CA-code unit 306 also controls the length of the integrationinterval. The observables are sampled on the MEO strobe. The data andthe address buses D and A are used by the microprocessor 101 to accessthe registers in the channel.

Within one AGGA 101 each CA-channel 30, 33, 36, 39, or CaP-channel 31,32, 34, 35, 37, 38, 40, 41, operating as a CA only channel, can beslaved to another channel as shown by the dashed or dotted lines in FIG.3. The signals which can be used in slaving are preferably AngleExt,CodeExt and CorrCtlExt (carrier rotation angle, the locally generatedcode and associated correlator control signals), respectively. It ispreferred in accordance with the present invention if not every channelcan be slaved with any other channel as this is wasteful of resourcesand brings little processing gain. The slave channel selection rule forthe channels shown in FIG. 3 may be summarized as follows: any channelCε(0 . . . N−1) may be slaved to a channel which satisfies (C−1 mod N)or (C−3 mod N). This means that a channel may either be a slave of itsprevious neighbor in the same column (or the bottom of the previouscolumn if C is at the top of a column) or be a slave of the channel inthe corresponding position in the previous column (or in the last columnif C is in the first column). The ability of the receiver in accordancewith the present invention to select one of at least two candidatechannel modules for the next module in a chain is a significantadvantage over the known receiver of U.S. Pat. No. 5,600,670.

FIG. 5 shows schematically an embodiment of the present invention havingone master 30 and two slave channels 33, 36 tracking CA-code onlymodulated signals. Each of the CA-channel 30, 33, 36 may be identical,components of the channels not used in this embodiment are not shown forclarity purposes. Alternatively, one or more of the channels 30, 33, 36may be CaP-channels 31, 32, 34, 35, 37, 38, 40, 41 of which only thecomponents are shown required for CA-code acquisition. Thisconfiguration can be used for fast CA-code acquisition and fordifferential carrier phase measurements in attitude determinationapplications. The carrier rotation angle (AngleOut) for all channels isgenerated by the master carrier NCO unit 304 and distributed to allslave channels 33, 36. Likewise, the code (CodeOut) and associatedcorrelator control signals (CorrCtlOut) for all channels 30-36 aregenerated by the master code unit 306 and distributed to the code delayline unit 338 of the first slave channel 33, which distributes thesesignals further down the chain.

In accordance with one embodiment of the present invention the replicaCA-code sequences may or may not be delayed by the code delay-line units308, 338, 368 of the master and slave channels 30, 33, 36 depending onthe application. In accordance with one embodiment of the presentinvention, the code delay-line units 308, 338, 368 may be programmeddifferently or fast acquisition and attitude determination,respectively. For fast acquisition, front-end input selector 302, 332,362 of all channels 30, 33, 36 are set to the same output of thefront-end 103 and all delay-line units 308, 338, 368 are programmed to ½or 1 CA-code chip delay. The correlator units 307, 337, 367 correlatethe individually delayed CA-code sequences with the received signal—themore channels process the same signal simultaneously, the fastersynchronization will be achieved. In accordance with one aspect of thepresent invention, the same signals from the front end 103 are processedby a selectable number of channels up to the maximum number of channelswhich can be assigned to the task of acquisition, hence resulting inrapid acquisition.

On the other hand, for attitude determination, all input selectors 302,332, 362 are set to a different front-end output (i.e., they all receivethe same basic signal but each one from a different antenna 104) and thedelay-line units 308, 338, 368 are programmed for zero delay, such thatall slave channels 33, 36 receive CA-code sequences from the masterCA-code unit 306 with identical phase. In one embodiment, the delay-lineunits such as 308 are selectable for one of a plurality ofpre-determined delays or for no delay depending upon the application.

As shown schematically in FIG. 6, a combined CA and P (CaP) channel,e.g., 31 or 32 contains all the functionality for CA-code operation asdescribed above with respect to FIGS. 3-5, e.g., the use of the imagereject mixers 315, 325, with additional enhancements to the correlatorunit (L1 demodulator) 317 and the correlator unit (L2 demodulator) 327for P-code and Y-code operation. A separate P-code unit 42-45 perdual-frequency channel generates the GPS and GLONASS P-codes and theirassociated integration control signals. Each CaP-code correlator unit317, 327 is specially adapted for the integration of P-code and Y-codesignals. More detail will be provided later with respect to codelessacquisition of the Y-coded signals in accordance with one embodiment ofthe present invention.

Normally a CA-channel such as 30 provides the carrier rotation angle forthe L1 P-channel such as 31. However, the L1 P-channel 31 can also useits internal carrier generator (not shown in FIG. 6 for 31 but similarto 324 of 32) to generate the carrier rotation angle (this may beadvantageous for better carrier phase performance in the presence ofmultipath). The correlator units 317, 327 of the CaP-channels 31, 32 arecontrolled by the CA-channel IntEpoch output signal, which is part ofthe CorrCtl bus. Hence the correlator units 307, 317, 327 of theCA-channel, the L1 P-channel and the L2 P-channel, respectively, of adual-frequency channel integrate over the same time period. The IntEpochsignal is also used for triggering the P-code generator during P-codeacquisition and is therefore also input directly into the P-code unit42. The rate at which the P-code for the L1 and L2 channels 31, 32 isgenerated is programmed in the code NCO's of the CA-code units 316, 326of the L1 P-channel 31 and of an L2 P-channel 32, respectively.

In accordance with one embodiment of the present invention, only twodual-frequency channels can be slaved in accordance with the rulesdefined by the dotted lines in FIG. 3. Such slaving doubles the numberof correlator units available for tracking the P-code on L1 and theP-code on L2, a feature which is provided for multipath mitigation (atthe cost of halving the number of available channels).

Some hardware is provided in accordance with the present invention toallow different groups of channels to be slaved together. The morepossibilities that are allowed for grouping together channels, thelarger the overhead on signal lines and multiplexers. Further, withcurrent clock frequencies, the sum of all delays which can be toleratedis limited by the repetition rate of the received signals. Hence, thechannel slaving requirements within one AGGA 10 in accordance with oneembodiment of the present invention are preferably up to foursingle-frequency channels or up to two dual-frequency channels. If achannel is configured to accept external carrier phase angle, code andcorrelator control signals, the slaving multiplexers of the channelmatrix 3 are preferably programmable to select the desired slavingsources. Selection may be done by means of multiplexers or selectorgates as shown schematically in FIGS. 7 a and 7 b. With reference toFIG. 4, the rotational angle for correction of the carrier phase may besupplied internally or externally, the selection being made by aselector circuit, e.g., a multiplexer 304. The external Angle signal maycome from one of two other previous channels depending on how theconnection in the slaving chain is formed, either the previous neighbor(C−1) or the one three back (C−3). Hence, as shown in FIG. 7 a, aselector circuit is provided, e.g., a multiplexer 29, which selectsbetween the Angle signal supplied by either the C−1 or C−3 channeldepending upon the AngleSel signal. Similarly, the selection betweenexternal or internal Code signals in FIG. 3 is made by a selectorcircuit, e.g., a multiplexer 303. Which external Code signal is selectedfor the channel 30 is determined by a selector circuit, e.g., amultiplexer 28 depending upon the CodeSel signal. The signals that canpreferably be slaved are Angle, Code (CA- or P-code) and various controlsignals grouped into CorrCtl, as shown in FIGS. 7 a and b. Two relatedsignals, DoubleChipRate and IntEpoch, are grouped as part of the CorrCtlbus to simplify the block diagrams.

The control circuitry shown in FIG. 7 b for a Ca-P channel moduleresembles that of FIG. 7 a, e.g., selectors 26 and 27 are equivalent toselectors 29 and 28 respectively. In one embodiment, a selector 25selects whether the P-code is taken from a P-code unit or is received inslaving mode. In one embodiment, a selector 24 controls whether theSignInSec is external or local. This signal will be described later withrespect to the extraction of Y-coded signals.

The code delay-line units such as 308 may produce Early (E), Punctual(P) and late (L) versions of the replica code and optionally a versionof IntEpoch. The code delay units in accordance with the presentinvention such as 308 may find general use in spread spectrum systems,e.g., in direct sequence CDMA. In accordance with an embodiment of thepresent invention, the delays between the E, the P and the L codeoutputs are programmable. The three code output sequences are used bythe correlator units such as 307 to despread the complex basebandsignal.

FIG. 8 shows schematically a code delay-line block diagram in accordancewith an embodiment of the present invention. A code delay-line unit,e.g., 308, selects three code phases E, P, L from a 13-stage delay-line52. The output sequences are spaced by multiples of either half a codechip or one CoreClk period. The former is only valid for code chip rateslower than one-quarter of the CoreClk rate. The clock source is selectedby a selector 54 to be either CoreClk or DoubleChipRate. The P versionof the Code is taken from one tap of the delay line 52. The delay fromthe input Code signal to the P version thereof is at least two DLClockperiods and at most seven DLClock periods (default value). CodeOut(passed to the next channel module in the chain if one exists) is eithera non-delayed or a delayed version of the code and is used for channelslaving. The selection between non-delayed and delayed is made in theselector circuit 56. For configuring channels for attitude determinationa zero delay between Code and CodeOut is selectable. By selectiveoperation of the two selector circuits 51 and 53 the delay from Code tothe delayed version of CodeOut can vary between two and thirteen DLClockperiods. By selective operation of selector circuits 51 and 55, thedelay from Code to E can vary between one and six DLClock periods.

Delay-line units such as 308 from several channels can be cascaded toproduce code sequences with delays larger than those possible with asingle delay-line 52. This feature is provided for rapid acquisition andmultipath mitigation. A switch control module 58 supports thetime-multiplexing of code sequences at different code spacings. Thistechnique can be used for multipath mitigation measuring of thecorrelation profile. It is however not preferred in applications withhigh-dynamics.

The ChipSpacingPL field of the DelayLineMode register (e.g., part ofon-chip memory) sets the chip spacing between the P and L codesequences. The following chip spacings between the E and P sequences orthe P and L sequences can be programmed using the selectors 51, 55, 57:T, 2T, 4T, 6T, and ½ chip, 1 chip, 2 chips or 3 chips, where T is theCoreClk period. As a consequence the following chip spacings between Eand L sequences can be programmed: 2T, 3T, 4T, 5T, 6T, 7T, 8T, 10T, 12Tand 1 chip, 1.5 chips, 2 chips, 2.5 chips, 3 chips, 3.5 chips, 4 chips,5 chips or 6 chips. The spacing in chips can only be used when theCoreClk frequency is at least four times the ChipRate. If this is notthe case the chip spacing in multiples of the CoreClk period ispreferably used.

The input selector 51 is used for cascading code delay-lines of slavedchannels. Its purpose is to provide a programmable delay between thecorrelation measurements of the slaved channels. Specifically, itenables a programmable chip spacing for fast acquisition and multipathmitigation. The input code sequence can be fed into tap 0 to 5 of thedelay-line 52. For correct behavior, the input selector 51 should selecta delay-line tap with a number lower than or equal to the number of thetap selected for the E sequence.

The cascading output CodeOut can be connected to one of taps 6 to 12 ofthe delay-line 51 or directly to the Code input. By connecting theoutput selection of one code delay-line unit to the input of anotherdelay-line unit, a single long delay line consisting of several slaveddelay-lines of different channels can be created. This output can beprogrammed independently of the chip spacing.

In accordance with one embodiment of the present invention, a switchcontrol functionality is used for time-sharing of a single correlatorover different code sequences. This allows the correlation profile to bemeasured without the need of extra correlators and is generallyapplicable to the despreading of spread spectrum signals. When thistechnique is used a different chip spacing (advance timing with respectto P) is selected for the E sequence by the selector circuit 55 at everyIntEpoch interval but a single correlator is used to accumulate theresults from each selection. The ability to selectively determine timingdifference, i.e., the delay or advance, between the E and P or P and Lsequences for each integration period is a significant advantage of oneembodiment of the present invention. One advantage of this method isthat the number of separate correlators required to measure thecorrelation profile is reduced. The timing sequence is controlled by theswitch control module 58. It is preferably fully programmable tosequence over two to four cycle periods. This includes the number oftime multiplexed taps (1 to 4) as well as the tap sequence. For example,for a switch sequence of three, the switch control sequence can beprogrammed to be T, 2T and 4T or T, 4T and 6T etc. The setting isbuffered into a register on an IntEpoch strobe so that themicroprocessor 101 can read to which E-P spacing the integration valuescorrespond. The IntEpoch strobe is used to synchronize the transitionsto the next switch setting to the integration interval. The provision ofa programmable switch 58 is a significant advantage of the presentinvention as it allows the sequential determination of correlationvalues for the E sequences at a different advanced timing with respectto the P sequence, hence allowing generation of a correlation profilewithout requiring a separate correlator for each different advancedtiming of the E sequence. Although embodiments of the present inventionhave been described with reference to the switch control module 58controlling the operation of the early delay line 55, another embodimentof the present invention includes a switch control module forcontrolling the operation of the late delay line 57 in a similar way.

FIGS. 9 a and 9 b show two examples of the slaving capability of theAGGA in accordance with the present invention. FIG. 9 a shows a possibleconfiguration with three channels configured for fast-acquisition. Thedelay lines 52, 52′ and 52″ are clocked by the DoubleChipRate signal.Nine complex integrators are configured to correlate nine code sequencesspaced by 0.5, 1, 1.5, 2, 2.5, 3, 3.5 and 4 code chips relative to thefirst E output tap. FIG. 9 b shows three delay lines 52, 52′ and 52″slaved for multipath mitigation. The nine correlators are configured tocorrelate nine code sequences being ET3, EE, E, E-L, P, L, LL, LT3, andLT4. With a CoreClk rate of 30 MHz, the E-L spacing is about 8/3 GPSP-code chips or 8/30 GPS CA-code chips.

The delay-line units such as 308 in accordance with one embodiment ofthe present invention support multipath mitigation in two ways: channelslaving and time-multiplexing. Channel slaving allows multiplecorrelators to be cascaded such that more samples of the correlationfunction can be obtained, FIG. 9 b shows an example of three channelswith slaved code delay-lines. The spacing between two adjacent sequencesis 4T. With a CoreClk of 20 MHz this is equivalent to 2 P-code chips.The right-most part of FIG. 9 b is performed in a despreader module of acorrelator unit.

A correlator unit block diagram in accordance with an embodiment of thepresent invention is shown in FIG. 10. A correlator unit such as 307 inaccordance with the present invention consists of a complex despreadermodule 62 and three complex integrator modules 64, 66, 68. Thedespreader module 62 multiplies the complex image reject mixer outputsignal (DataIn) with three code sequences. Each integrator module 62,64, 66 integrates a despread data-sequence over a programmableintegration interval equal for all integrators 62, 64, 66 of acorrelator unit 307.

The despreader module 62 multiplies the complex baseband signal by threecode sequences. Each code sequence is a combination of the threespreading code sequences E, P and L. Valid combinations of the codesequences E, P and L are: (P,E,L), (P,E-L,Off), (P,E-L,E), (P,E-L,L),(P,P,Off) and B,Off,Off) with Off representing “not used” and Brepresenting “bypassed.” The principal usage for the differentcombinations of code sequences are:

-   -   (P,E,L): This combination is used for fast acquisition or for        measuring absolute correlation values of a data sequence        despread with E, P and L code sequences e.g. for multipath        mitigation techniques. Also tracking with separate E and L        measurements uses this combination.    -   (P,E-L,Off): This combination is used in tracking mode and when        no information about the absolute E or L correlation values is        needed.    -   (P,E-L,E): This combination is used in tracking mode for        multipath identification. An extra E measurement is obtained        when three channels are slaved equivalent to FIG. 9(b).    -   (P,E-L,L): This combination is used in tracking mode for        multipath identification. An extra L measurement is obtained        when three channels are slaved as shown in FIG. 9(b).    -   (P,P,Off): This combination only uses the P sequence. This is        used in the slave channel configured for hybrid        parallel-multiplex attitude determination mode.    -   (B,Off,Off): This combination is used in calibration mode. The        despreader 62 is bypassed and only the first integrator is used.        The output of the despreader module 62 are three complex        sequences of despread data DesprValue1-3. The I and Q value of        DesprValue is either −3, −1, 0, 1 or 3. The value 0 will only        occur in E-L configuration, in which case the correlation values        are also divided by two.

An integrator module 64, 66, 68 in accordance with one embodiment of thepresent invention is a complex integrator. In one embodiment, theintegrator module 64, 66, 68 may find general application in thedespreading of spread spectrum signals, e.g., in direct sequence CDMAreceivers. The correlator unit of a CA-channel contains CA-codeintegrators while the correlator unit of a CaP-channel contains CaP-codeintegrators. A block diagram of the CA-code integrator module 70 inaccordance with one embodiment of the present invention is shown in FIG.11.

In one embodiment, a CA-code integrator acts as a 22-bit adder. Inanother embodiment, the CA-code integrator is a two-stage integratorconsisting of a low number of bits accumulator, e.g., a 9-bit two'scomplement primary accumulator 72 and a full number of bits accumulator,e.g., a 22-bit two's complement secondary accumulator 74. The result ofthe primary accumulator 72 is dumped at a rate equal to the CA-code chiprate into a first integration buffer 73. The second accumulator 74integrates the dumped contents of the first accumulator 72 over a longerperiod, e.g., one IntEpoch period. The result is double buffered in asecond integration buffer 75 and kept until the end of the nextintegration period, when it will be overwritten by the new integratorvalue. One advantage of this two-stage integration is the fact that thepower consumption can be reduced dramatically. Only the small primaryaccumulator 72 is operating at the high clock rate, while the largesecondary accumulator 74 is only running at the chip rate. The use of atwo-stage integrator for the CA-code is one of the major advantages ofthe present invention compared to the known integrators of EP 508 621.

In hybrid parallel-multiplex attitude determination mode, theintegration values can also be stored into the secondary accumulatorintegration buffers 75 on an ASE strobe. Together with the selection ofthe (P,P,Off) code sequence combination in the despreader module 62, onecomplex integrator 64, 66, 68 will be programmed to update the secondaryaccumulator integration buffers 75 on an IntEpoch strobe while the otherenabled complex integrator 64, 66, 68 will update the integrationbuffers on an ASE strobe. The integrators themselves are then reset atboth IntEpoch and ASE strobes.

A CaP-code integrator module 80 in accordance with one embodiment of thepresent invention can be configured to accumulate CA-code modulatedsignals, P-code modulated signals or encrypted P-code modulated signals,i.e., Y-code modulated signals. A block diagram of the CaP-codeintegrator module according to this embodiment is shown in FIG. 12. ACaP-code integrator 80 in accordance with one embodiment of the presentinvention consists of a low number of bits primary accumulator, e.g., a9-bit two's complement primary accumulator 82 and a full number of bitssecondary accumulator, e.g., a 22-bit two's complement secondaryaccumulator 84. In normal operation both accumulators 82, 84 will neveroverflow and no data will be lost between the primary and secondaryaccumulator. The following operational modes can be distinguished:

CA-mode: the CaP-code integrator 80 is configured to track CA-codemodulated signals and behaves identically to the CA-code integratormodule 70 described above. The primary accumulator 82 results are dumpedat a rate equal to the CA-code chip rate into an integration buffer 83.The secondary accumulator 84 is configured to be an adder only and isalways enabled.

Attitude determination mode: In attitude determination mode, theCaP-code integrator 80 is rest both on the IntEpoch and ASE strobe. Thismode corresponds to the (P,P,Off) despreader mode.

P-mode: The CaP-code integrator 80 is configured to track P-codemodulated signals. The only difference between the CA-mode and theP-mode is the control of the primary dump logic 81. The SecondaryEnablestrobe controls the transfer of the primary accumulator contents to thesecondary accumulator 84, while the WChipEdge strobe controls bufferingand reset of the primary accumulator 82. The secondary accumulator 84 isconfigured to be an adder only and is always enabled (EnableSel is 0).The secondary accumulator integration buffers 85 are updated on thecommand of the IntEpoch strobe.

Y-mode: In the Y-mode, a signal is received which consists of a P-codemodulated with an unknown W-code. An exact despreading is not possible,hence one embodiment of the invention estimates the W-code sufficientlyto obtain the timing and phase data of the received signals. To decodesuch a signal, a W-code estimation capability is provided between theprimary and secondary accumulator 82, 84 of a dual-frequency channel inaccordance with one embodiment of the present invention, as shownschematically in FIG. 13. There are several modes in which the CA-Pintegrator module 80 can process W-coded and P-coded signals each ofwhich is an embodiment of the present invention.

Generally, the primary accumulator 82L1, 82L2 of each channel L1 and L2integrates the incoming data (possibly despread with the known P-code)over one W chip period (generated in the W-rate generator describedlater). Based on this result, the W-Code Estimation unit 86 estimatesthe corresponding value of the W-rate.

Codeless Squaring: Functionally the CaP-Code integrator 80 operates as asingle adder which adds a sequence of samples over an IntEpoch period.This codeless squaring technique requires a circuit (not shown) thatsquares the incoming signal before the adding operations. Incomingsamples which have not be despread by the locally generated P-codereplica sequence are integrated in the primary accumulators 82L1, 82L2over a time period, e.g. one W-code interval (assumed known) signaled byWchipEdge. The primary and secondary accumulators 82, 84 (82L1, 82L2;84L1, 84L2) are configured in add mode and are always enabled. Thesecondary integration buffers 85 are updated on IntEpoch strobes.

Coded Squaring: Functionally the primary accumulator 82 operates as anadder which adds a sequence of despread (with a locally generatedreplica of the P-code) samples over one W-code interval signaled byWchipEdge. The secondary accumulator 84 operates as an adder which addsthe absolute values of the primary accumulator 82. The secondaryaccumulator 84 is configured to add absolute primary accumulation valuesby selecting the SignInSec input bit (this is a kind of “squaring”).This bit is preferably the sign bit of the value from the Q-branch ofthe complex primary accumulator 82 which is processing the “punctual”code replica (P of E, P, L) of the first integrator 82 (this branchnormally has the highest strength of the relevant signal but the presentinvention is not limited thereto). The secondary accumulator integrationbuffers 85 are updated on IntEpoch strobes.

Coded cross-correlation: Functionally the primary accumulator 82operates as an adder which adds a sequence of despread (with a locallygenerated replica of the P-code) samples over one W-code intervalsignaled by WchipEdge. The secondary accumulator 84 operates as an adderwhich adds the primary values of an L1 (alternatively L2) channelmultiplied by the sign bit of the L2 (alternative L1) primaryaccumulator. The secondary accumulator 84 is configured to add absoluteprimary accumulation values by selecting the SignInSec input bit. For anL1 (L2) channel this bit is the sign bit of the Q-branch of the complexprimary accumulator value of the first integrator 82 of the L2 (L1)channel. The secondary accumulator 84 is enabled by the SecondaryEnablestrobe generated by the P-code generator unit. The secondary accumulatorintegration buffers 85 are updated on IntEpoch strobes.

Combined Y-code estimate: In a further embodiment of the presentinvention, the primary accumulator 82 operates functionally as an adderwhich adds a sequence of despread (with a locally generated replica ofthe P-code) samples over one W-code interval signaled by WchipEdge. Thesecondary accumulator 84 operates as a combiner which combines theprimary values of the primary accumulator 82 and the estimated W-codechip. One method of combining includes summing the values output by theprimary accumulator 82 multiplied by the estimated W-code chip value.However, one embodiment of the present invention includes other methodsof combining. For instance, one embodiment includes combining theoutputs of the primary accumulator 82 in dependence upon a confidencelevel in each output from accumulator 82. The estimated W-code chip isobtained by comparing the absolute values of the primary accumulator ofthe Q-branch of the complex primary accumulator value of the firstintegrator 82 of the L1 and L2 channel. The estimated W-code chip value(or Y-code value) is the sign bit of the largest value from thiscomparison. Because of the lower transmit power, a scaling value may beapplied to the L2 signal which is usually more powerful than the L1signal. A value of 0.75 is suitable. The secondary accumulatorintegration buffers 85 are updated on IntEpoch strobes. FIG. 14 showsone embodiment of the selection logic required to provide the Y-codeestimate indicated above. The outputs of the primary accumulators 82L1and 82L2 for the L1 and L2 channels, respectively are applied toabsolute value circuits 861, 862, respectively, whereas the sign of eachof these primary accumulated outputs is transferred to a Y-code estimateselector (or W-code chip estimate selector) 865. In the absolute valuecircuits 861, 862 the absolute value of the respective primaryaccumulator value is determined. The absolute value output from circuit862 may be modified to allow for received power differences between theL1 and L2 signals, e.g., it can be multiplied by a factor such as 0.75(multiplier 864). The modified absolute values are input to a comparator864 which compares the two absolute values and outputs a signal to aY-code estimate selector 865 indicating which of the signals from L1 orL2 has the largest absolute value. The selector 865 selects the sign ofthe signal with the largest absolute value as the value for the W-codechip or, optionally, an alternative value. The optional alternativevalue may be zero, e.g., when the confidence in the result is low. Theoutput for the Y-code estimate selector 865 is combined with each of theprimary accumulated values of the L1 and L2 accumulators 82L1 and 82L2for use in the secondary accumulators 84L1 and 84L2 respectively.

A P-code unit such as 42 in accordance with one embodiment of thepresent invention has two main functions: generating the replicas of theGPS and GLONASS P-code sequences for L1 and L2 and generating the W-codeintegration control strobe signals (WChipEdge) for L1 and L2. The latteris used for tracking the GPS Y-code signal with the coded squaring, thecoded cross-correlation technique and other techniques described aboveparticularly the combined Y-code estimate embodiment of the presentinvention. One P-code unit 42-45 is provided per dual-frequency channel.

The P-code sequence and the sequence of W-code integration controlstrobes are the same for L1 and L2 but with a relative delay due todifferent ionospheric and front-end group delays at the two frequenciesL1 and L2. The total group delay difference between L1 and L2 does notexceed 1 microsecond. This delay is the sum of the maximum specifiedionospheric group delay of 800 ns between L2 lagging L1 and 200 ns dueto front-end group delays. L1 can only lag L2 due to different front-endgroup delays. Hence the total group delay between L1 and L2 can varybetween −200 ns and 1 microsecond. A delay of 1 microsecond isequivalent to 10 GPS P-code chips or 5 GLONASS P-code chips, while 200ns corresponds to 2 GPS P-code chips or 1 GLONASS P-code chip. Thesenumbers are a factor of 10 lower for CA-code chips.

A P-code unit block diagram in accordance with an embodiment of thepresent invention is shown in FIG. 15. Its main modules are the P-codegenerator 92, the W-rate generator 94, the cycle difference counter andswitch controller 96, the P-code and WChipEdge delay-lines 91, 93 andthe sequence switches 95, 97, 99. The P-code generator 92 containsfunctionality for generating replicas of the GPS and GLONASS P-codesequences, P-code observables, and functionality to initialize the Pcode and perform P-code handover which controls the enabling of theP-code. Because both code sequences are delayed versions of the samecode, a single P-code generator 92 and a single W-Rate generator 94 withadditional delay-line 93, and control and switching logic is used toproduce both sequences for L1 and L2. The lagging sequence is obtainedfrom a delay-line 91, 93 controlled by the cycle difference counter 96while the other is taken directly from the generator output which is thereplica of the P-code and the W chip edge, respectively. The cycledifference counter 96 records the phase difference between the L1 P-codesequence and the L2 P-code sequence as an integer number of code chips.This phase difference is the same for the L1, L2 W chip edges. Aninitial difference is programmed by the microprocessor 101 andrepresents the relative delay of the L1 and the L2 sequences. It is theaccurate determination of this difference which needs to be performed bythe acquisition software. The switch control and the switches 95, 97, 99enable the microprocessor 101 to select which of the two L1 or L2sequences of P-code and W chip edges is lagging the other.

The GLONASS P-code is a binary sequence with a nominal chip rate of 5.11MHz generated by the code NCO and a sequence duration of precisely onesecond. The P-code is the tenth tap of a 25-tap linear feedback shiftregister (LFSR) with generating polynomial defined as:G _(P)=1+X ³ +X ²⁵The code sequence is short-cycled to a length of 5,110,000 chips, thiscorresponds to the LFSR state of “0CBE669” hexadecimal. The initialstate of the P-code generator is a vector of 25 ones. This statecoincides with the one-second mark in the GLONASS navigation message.

The GPS P-code is a binary sequence with a nominal chip rate of 10.23MHz generated by the code NCO and a sequence duration of precisely oneweek. The GPS P-code is a modulo-2 addition of two sequences, the X1sequence and the X2 sequence. The code for SV is obtained by delayingthe X2 sequence by chips prior to modulo-2 addition to the X1 sequence,where is a value ranging from 1 to 37. The X1 code is generated by themodulo-2 addition of two short-cycled maximum-length sequences, whosegenerating polynomials are defined as:X1A=1+X ⁶ +X ⁸ +X ¹¹ +X ¹²X1B=1+X ¹ +X ² +X ⁵ +X ⁸ +X ¹⁰ +X ¹¹ +X ¹²The X1A sequence is short-cycled to a length of 4092, while the X1Bsequence is short-cycled to a length of 4093. The X1 sequence has aperiod of 3750 X1A periods, which is equal to 15,345,000 P-code chips or1.5 seconds. When the X1B LFSR completes its 3749th period it is haltedfor the duration of 343 chip periods (until the X1A LFSR completes its3750th period). On completion of each X1 period both X1 LFSRs are resetto their initial states as defined in table 1. The X1 epoch indicatesthe end of each X1 period.

Similar to the X1 code, the X2 code is generated by the modulo-2addition of two short-cycled maximum-length sequences, whose generatingpolynomials are defined as:X2A=1+X ¹ +X ³ +X ⁴ +X ⁵ +X ⁷ +X ⁸ +X ⁹ +X ¹⁰ +X ¹¹ +X ¹²X2B=1+X ² +X ³ +X ⁴ +X ⁸ +X ⁹ +X ¹²

The X2A sequence is short-cycled to a length of 4092, while the X2Bsequence is short-cycled to a length of 4093. Similar to the X1sequence, the X2 period contains 3750 X2A periods. When the X2B LFSRcompletes its 3749th period it is initially halted for the duration of343 P-code chip periods. When the X2A LFSR completes its 3750th periodit is also halted. Subsequently, both X2A and X2B LFSRs are halted for afurther duration of 37 P-code chip periods, causing the X2 period to be37 chip periods longer than the X1 period. After this delay, the X2A andX2B LFSRs are reset to the initial states shown in Table 1. TABLE 1 LFSRinitial state X1A 001001001000 X1B 010101010100 X2A 100100100101 X2B010101010100

The Z counter which is located in the P-code units such as 42, is a19-bit counter with a valid range of 0 to 403,199 (period of 403,200).This counter counts the number of elapsed X1 epochs since the start ofthe week, commonly referred to as the Z count. In its final state the Zcounter signals End Of Week (EOW). During the last X1A period of a week,and after reaching their final state, the X1B, X2A and X2B generatorswill be halted until the X1A generator reaches its final state. Thefinal X1A epoch causes all generators to be restarted from theirrespective initial states and the Z count to be reset to 0.

When the initialization process of the P-code generator 92 is triggered,the X1 generator is initialized to the initial states shown in table 1.To establish the correct relative phase between the X1 and X2 sequencescorresponding to the programmed Z count, the X1 generator isautomatically clocked for 37 times the Z count. After the X1 generatorreaches its correct state the X2 generator is initialized to the initialstates shown in table 1. Subsequently, both generators are clocked untilthe occurrence of an X1 epoch and then halted. This initializationprocess takes a number of cycles equivalent to exactly a full X1 periodof 1.5 s, i.e., 15,345,000 cycles.

After the P-code generator 92 has been initialized the P-code handoverstarts the generation of a P-code sequence at the correct time instance.This mechanism requires hardware-firmware interaction. Afterinitialization, the P-code generator 92 should not be enabled until thefirst bit of the preamble of the next subframe has been received. Asdecoding of the navigation data is a firmware task, this event must besignaled by the firmware. The P-code generator 92 is then enabled on thefollowing active IntEpoch. After hand-over the setting is automaticallyreset.

The P-code observable is used to find a high-precision pseudorange. Itis obtained from a 24-bit counter, which counts the number of P-codechips. It is reset after reaching a count equal to the nominal number ofP-code chips per second for GLONASS and per 1.5 seconds for GPS. Thisnumber is equal to 5,110,000 GLONASS P-code chips or 15,345,000 GPSP-code chips. At the end of each measurement epoch the P-code chip countis stored in an observable register. The P-code chip counter is reset atP-code hand-over.

The W-rate generator 94 generates the control strobes for dumping theprimary accumulator stages of the CaP-integrator modules 80. It is aprogrammable 5-bit decrementer which counts P-code chips. Each time thedecrementer reaches 0, a WChipEdge strobe is generated and thedecrementer is reloaded. M strobes are generated with a period of AP-code chips followed by N strobes at a rate of B P-code chips. Thesequence is repeated until an X1A-epoch, generated by the P-codegenerator. The start of a new sequence can be delayed by S P-code chips.

The cycle difference counter 96 is a 5-bit counter that keeps track ofthe delay between the L1 and L2 P-codes, expressed in P-code chips. Inconjunction with the variable delay-line 91, 93, it derives a delayedversion of a P-code sequence. Similar to the P-code, L1 and L2 W-codechip edges are generated from a single W rate generator 94. The switchcontroller 96 keeps track of which sequence L1 or L2 is lagging theother. The change in phase difference is further controlled indirectlyby programming the frequency and phase of the code NCO's driving theP-code generator 92, which are the clock signals triggering the cycledifference counter and the switch controller 96. When the L1 code NCO(not shown, located in the CA-Code generators) produces a clock pulse aprogrammable counter is incremented and when the L2 code NCO products aclock pulse it is decremented. When both NCOs generate a clock pulse thecounter is inhibited. To prevent incorrect control of the delay-line 91,93 the cycle difference counter is inhibited when it reaches its maximumdelay of 10.

Due to front-end group delay differences between the L1 and L2 RFsections, the L2 P-code may lead the L1 P-code. Therefore, it ispossible to delay the L1 P-code relative to the L2 P-code byinterchanging the L1 and L2 inputs and associated outputs whenever theL1-L2 delay crosses zero. This functionality is controlled by the switchcontroller 96 and the associated switches 95, 97. The use of delay line91 with only delayed timings and the switch 95 to switch between the L1and L2 signals reduces the size of delay line 91 compared toconventional designs which is a significant advantage compared with thecorrelator known from EP 508 621.

The cycle difference counter 96 is programmed on an IntEpoch strobe. Thevalue of the cycle difference counter 96 is an observable which isstored at the end of each measurement interval, i.e., at the same timeas the other code and carrier phase observable registers. The L1-L2delay observable is obtained by summing the contents of this observableand the difference of the L1 and L2 code NCO phase registers.

In each P-code unit 90, there is one P-code delay line 91 and one W-ratedelay line 93 of length 10. Both delay lines 91, 93 are clocked by thechip rate of the leading sequence shifting the bits in the delay-line91, 93 similar to a first-in-first-out buffer. Its input is a P-codechip for the P-code delay line 91 and a W-edge for the W-rate delay line93. The output is a tap of 1 to 10 controlled by the cycle differencecounter 96. A cycle difference counter value of zero selects the inputof the delay line 91, 93.

While the above description has pointed out novel features of theinvention as applied to various embodiments, the skilled person willunderstand that various omissions, substitutions, and changes in theform and details of the device or process illustrated may be madewithout departing from the scope of the invention. Therefore, the scopeof the invention is defined by the appended claims rather than by theforegoing description. All variations coming within the meaning andrange of equivalency of the claims are embraced within their scope.

1. A method of processing received L1 and L2 spread spectrum signals,wherein each of the signals includes a unique frequency carrier with aknown pseudo-random code modulated thereon, each L1 and L2 signal beingconverted into a plurality of digital signals, the method comprising:locally generating a single replica of the known code; making the codereplica available at different relative phases; first demodulating theconverted L1 and L2 signals with the single replica of the known codewithout any substantial delay, the first demodulated signal beingassociated with the L1 signal; second demodulating the converted L1 andL2 signals with the generated replica of the known code from one of thetaps of the delay line, the second demodulated signal being associatedwith the L2 signal; selectably switching the converted L1 and L2 signalsfor the first demodulation and selectably switching the converted L1 andL2 signals for the second demodulation; repetitively and separatelyintegrating the demodulated L1 and L2 signals over a time period; andadjusting the phases of the locally generated code replicas relative tothe incoming L1 and L2 signals in order to maximize the power of theintegrated demodulated L1 and L2 signals.
 2. The method according toclaim 1, wherein the resulting locally generated code phases are useableto determine information of the location of a receiving position withhigh accuracy.
 3. The method according to claim 1, wherein the frequencycarriers are also modulated with an unknown code and the phaseadjustment includes: correlating an integration result for one of the L1and L2 signals with an integration result for the other of the L1 and L2signals; and adjusting the phases of the locally generated known codereplicas relative to the incoming L1 and L2 signals in order to maximizethe power of the correlated L1 and L2 signals, wherein the resultinglocally generated known code phases are useable to determine informationof the location of a receiving position.
 4. The method according toclaim 1, wherein the integrating of the demodulated L1 and L2 signalscomprises: first integrating the demodulated signals over a firstpredetermined period of time; and second integrating the firstintegrated signals over a second predetermined period of time longerthan the first predetermined period of time.
 5. The method according toclaim 1, wherein the received L1 and L2 spread spectrum signals arereceived from at least one of a Global Positioning System (GPS) andGlobal Orbiting Navigation Satellite System (GLONASS).
 6. An apparatusfor processing received L1 and L2 spread spectrum signals, wherein eachof the signals includes a unique frequency carrier with a knownpseudo-random P-code and an unknown code modulated thereon, theapparatus comprising: a generator of replicas of the known P-code; adelay line configured to make the known P-code replicas available atdifferent relative phases; a first demodulator, connected to thegenerator, configured to demodulate one of the received L1 and L2signals with one of the known P-code replicas; a second demodulatorconfigured to demodulate the other of the received L1 and L2 signalswith one of the known P-code replicas; a first integrator configured torepetitively and separately integrate the demodulated one of the L1 andL2 signals over time periods related to the unknown code; a secondintegrator configured to repetitively and separately integrate thedemodulated other of the L1 and L2 signals over time periods related tothe unknown code; and a correlator configured to correlate the firstintegrator output with the second integrator output.
 7. The apparatusaccording to claim 6, wherein the correlator includes: a comparatorconfigured to compare the absolute values of the integrated demodulatedL1 and L2 signals; a combiner configured to individually combine thevalues of the integrated demodulated L1 and L2 signals with a unitaryvalue having the largest value as output by the comparator; a firstaccumulator configured to individually and separately accumulate thecombined values for the demodulated one of the L1 and L2 signals; and asecond accumulator configured to individually and separately accumulatethe combined values for the demodulated other of the L1 and L2 signals.8. The apparatus according to claim 7, further comprising a phaseadjuster configured to adjust the phases of the locally generated P-codereplicas relative to the incoming L1 and L2 signals in order to maximizethe power of the correlated L1 and L2 signals.
 9. The apparatusaccording to claim 7, wherein the combiner comprises a multiplier. 10.The apparatus according to claim 7, wherein the first accumulatoroperates functionally as an adder and the second accumulator operates asa combiner.
 11. The apparatus according to claim 6, wherein theapparatus is for use with at least one of a Global Positioning System(GPS) and Global Orbiting Navigation Satellite System (GLONASS).
 12. Anapparatus for processing received L1 and L2 spread spectrum signals,wherein each of the signals includes a unique frequency carrier with aknown pseudo-random code modulated thereon, each L1 and L2 signal beingconverted into a plurality of digital signals, the apparatus comprising:a generator configured to locally generate a single replica of the knowncode; a delay line wherefrom the known P-code replicas are available atdifferent relative phases thereof, wherein the single replica of theknown code is applied to the delay line; a first demodulator configuredto first demodulate the converted L1 and L2 signals with the singlereplica of the known code without any substantial delay, the firstdemodulated signal being associated with the L1 signal; a seconddemodulator configured to second demodulate the converted L1 and L2signals with the generated replica of the known code from one of thetaps of the delay line, the second demodulated signal being associatedwith the L2 signal; a switch configured to selectably switch theconverted L1 and L2 signals for the first demodulation and selectablyswitch the converted L1 and L2 signals for the second demodulation; anintegrator configured to repetitively and separately integrate thedemodulated L1 and L2 signals over a time period; and a phase adjusterconfigured to adjust the phases of the locally generated code replicasrelative to the incoming L1 and L2 signals in order to maximize thepower of the integrated demodulated L1 and L2 signals.
 13. A method ofprocessing received L1 and L2 spread spectrum signals, wherein each ofthe signals includes a unique frequency carrier with a knownpseudo-random P-code and an unknown code modulated thereon, the methodcomprising: locally generating replicas of the known P-code; making thecode replicas available at different relative phases; demodulating thereceived L1 and L2 signals with replicas of the P-code; repetitively andseparately integrating the demodulated L1 and L2 signals over timeperiods related to the unknown code; and correlating an integrationresult for one of the L1 and L2 signals with an integration result forthe other of the L1 and L2 signals.
 14. The method according to claim13, further comprising adjusting the phases of the locally generatedP-code replicas relative to the incoming L1 and L2 signals in order tomaximize the power of the correlated L1 and L2 signals.
 15. The methodaccording to claim 14, wherein the correlating comprises: comparing theabsolute values of the integrated demodulated L1 and L2 signals;individually combining the values of the integrated demodulated L1 andL2 signals with a unitary value having the largest value as determinedin the comparing; and individually and separately accumulating thecombined values.
 16. The method according to claim 15, wherein thecombining comprises multiplying.
 17. The method according to claim 13,wherein the received L1 and L2 spread spectrum signals are received fromat least one of a Global Positioning System (GPS) and Global OrbitingNavigation Satellite System (GLONASS).
 18. The method according to claim13, wherein the resulting locally generated P-code phases are useable todetermine information of the location of a receiving position.
 19. Asystem for processing received L1 and L2 spread spectrum signals,wherein each of the signals includes a unique frequency carrier with aknown pseudo-random code modulated thereon, each L1 and L2 signal beingconverted into a plurality of digital signals, the system comprising:means for locally generating a single replica of the known code; meansfor making the code replica available at different relative phases;means for first demodulating the converted L1 and L2 signals with thesingle replica of the known code without any substantial delay, thefirst demodulated signal being associated with the L1 signal; means forsecond demodulating the converted L1 and L2 signals with the generatedreplica of the known code from one of the taps of the delay line, thesecond demodulated signal being associated with the L2 signal; means forselectably switching the converted L1 and L2 signals for the firstdemodulation and selectably switching the converted L1 and L2 signalsfor the second demodulation; means for repetitively and separatelyintegrating the demodulated L1 and L2 signals over a time period; andmeans for adjusting the phases of the locally generated code replicasrelative to the incoming L1 and L2 signals in order to maximize thepower of the integrated demodulated L1 and L2 signals.